The present invention relates to a flash memory cell and methods of manufacturing same. More particularly, the present invention relates to a flash memory cell with less susceptibility to charge gain and charge loss.
Integrated circuits (ICs), such as ultra large scale integrated (ULSI) circuits, can presently include more than one million transistors. ICs can include various devices such as complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) and flash memory cells.
A flash memory cell is generally comprised of a transistor connected to a word line and a bit line. The transistor includes a gate stack comprised of a polysilicon cap, a control gate, a control gate dielectric, a floating gate, and a tunnel dielectric. The polysilicon cap is disposed over the control gate, and the control gate is disposed over the control gate dielectric. The control gate dielectric is disposed over the floating gate, and the floating gate is disposed over the tunnel dielectric. The transistor further includes a source and a drain; the gate stack is disposed between the source and drain. The transistor still further includes an insulative spacer which abuts each side of the gate stack. The bit line connects to the drain of the transistor via a contact coupled to the drain. The word line connects to the control gate of the transistor. Voltages applied to specific parts of the flash memory cell allow storage and erasure of date (e.g., a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) in the floating gate.
The transistor can be covered by a high temperature oxide (HTO) layer and an interlevel dielectric to insulate it from subsequently formed metal layers. An aperture or hole is etched through the interlayer dielectric and the high temperature oxide. The hole is filled with a conductive material to provide connections to the transistor, to conductors, or to other circuit structures. For example, a contact can extend from the bit line through the interlevel dielectric to the drain of the transistor. In another example, a contact or conductive via can extend through the interlevel dielectric to connect to the gate stack.
One problem associated with memory cell transistors is charge loss or charge gain. Charge loss or gain can occur from electrons traveling through the high temperature oxide or interlayer dielectric between the contact and the floating gate. Such charge gain or loss in the floating gate can destroy the data stored in the memory cell. Susceptibility to charge gain or loss increases as the distance between contacts and floating gates decreases or when gate stacks are not properly protected from moisture or hydrogen diffusion.
Distances between contacts and floating gates have become smaller as transistors disposed on integrated circuits have become smaller (e.g., transistors with gate lengths approaching 50 nanometers (nm)) so that a greater density of such transistors can be included in each integrated circuit. Moreover, high temperature oxide, as described above, is typically deposited over the gate stack as a protective layer against moisture or hydrogen diffusion. High temperature oxide, however, is not the most effective blocking layer against depletion of hydrogen or moisture from moisture or hydrogen diffusion and as such aggravates the charge gain or loss problem.
Thus, there is a need for an integrated circuit that has less susceptibility to charge gain and loss problems. Further still, there is a need for a method of manufacturing a transistor that is less susceptible to charge gain and charge loss. Even further still, there is a need for a flash memory cell that includes an apparatus designed to simultaneously provide better blocking capability against moisture or hydrogen diffusion and also increases the contact-to-floating gate distance, thereby reducing charge gain and charge loss.
One exemplary embodiment relates to an integrated circuit including a plurality of transistors. Each of the plurality of transistors include a gate stack and the plurality of transistors are at least partially covered by a capping layer and an interlevel dielectric. A hole extends through the capping layer and the interlevel dielectric. The configuration of the capping layer and the hole makes the integrated circuit less susceptible to charge gain or charge loss associated with the gate stacks.
Another exemplary embodiment relates to an integrated circuit including a first transistor and a second transistor having a first gate stack and a second gate stack, respectively. The integrated circuit further includes a capping layer disposed over the first gate stack, the second gate stack, and at least a first portion of the base layer between the first gate stack and the second gate stack. The integrated circuit still further includes an interlevel dielectric disposed over the capping layer, and a contact substantially disposed between the first and second gate stacks. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer.
A further exemplary embodiment relates to a method of manufacturing an integrated circuit. The method includes providing a gate stack on a base layer, providing a capping layer over the gate stack and the base layer, and providing an interlevel dielectric over the capping layer. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer. The method further includes etching the buffer layer, the first insulative layer, the second insulative layer, and the interlevel dielectric to form a hole extending to the base layer, wherein the hole includes at least one of a width wider at the interlevel dielectric than at the buffer layer and a step-like feature near the base layer.